There is a constant push in the semiconductor industry towards reducing the size of semiconductor integrated circuits (ICs), which requires the reduction in semiconductor device geometry and interconnect lines connecting the semiconductor devices. Furthermore, the spacing between interconnect lines and adjacent semiconductor devices must also be reduced to fully achieve smaller ICs. However, as the spacing between interconnect lines and semiconductor devices is reduced to the micron and submicron range, a parasitic intra-level capacitance between the interconnect lines and adjacent devices increases. Consequently, in order to reduce cross-talk between interconnect lines and semiconductor devices and to maximize semiconductor device speed it becomes increasingly important to reduce the parasitic capacitance between interconnect lines and semiconductor devices. In fact, in many cases, the intra-level capacitance of metal interconnect lines has become the limiting factor in determining the speed of many silicon ICs.
One approach to reduce the intra-level capacitance involves increasing the spacing between the interconnect lines and adjacent semiconductor devices. However, this proposed solution is not compatible with the original goal of shrinking the size of semiconductor ICs.
A second approach to reduce the intra-level capacitance involves using a low dielectric constant material between the interconnect lines and adjacent semiconductor devices. A third approach involves depositing a first dielectric layer, etching away the initial dielectric material deposited between the interconnect lines and the semiconductor devices, and refilling the etched away portion with a different low dielectric constant polymer. The second and third proposed solutions produce detrimental side effects and may not sufficiently reduce the intra-level capacitance of the IC. With the use of increasingly small spacing between the interconnect lines and semiconductor devices, the low dielectric constants of many dielectric materials are often not low enough to significantly reduce the parasitic inter-level capacitance. Moreover, the process steps associated with incorporating these dielectrics into a conventional process flow are time consuming, complicated, and expensive. The resulting structure also may reduce the efficiency of heat dissipation since materials having lower dielectric constants generally have lower thermal conductivity. Furthermore, the resulting structure creates other reliability problems that include, but are not limited to, moisture absorption, adhesion failures, and mechanical stress failures.
Thus, there is a need for improved structures that reduce the parasitic capacitance between interconnect lines and adjacent semiconductor devices without the drawbacks described above. Accordingly, a need exists for a device that is structurally sound, is not expensive to manufacture and does not cause a significant increase in the cycle time of the manufacturing process flow. The method should also not impede thermal dissipation and should be compatible with shrinking the size of semiconductor ICs.